134_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

134_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Design for Testability 103 [Savir 1994] J. Savir and S. Patil, Broad-side delay test, IEEE Trans. Comput.-Aided Design , 13(8), 1057–1064, 1994. [Stewart 1978] J. H. Stewart, Application of scan/set for error detection and diagnostics, in Proc. Semiconductor Test Conf. , October 1978, pp. 152–158. R2.9—RTL Design for Testability [Aktouf 2000] C. Aktouf, H. Fleury, and C. Robach, Inserting scan at the behavioral level, IEEE Des. Test Comput. , 17(3), 34–42, 2000. [Ghosh 2001] I. Ghosh and M. Fujita, Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams, IEEE Trans. Comput.- Aided Des. , 20(3), 402–415, 2001. [Huang 2001] Y. Huang, C. C. Tsai, N. Mukherjee, O. Samoan, W.-T. Cheng, and S. M. Reddy, On RTL scan design, in Proc. Int. Test Conf. , November 2001, pp. 728–737. [Ravi 2001] S. Ravi and N. Jha, Fast test generation for circuits with RTL and gate-level views, in Proc. Int. Test Conf ., November 2001, pp. 1068–1077.
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.
Ask a homework question - tutors are online