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CHAPTER 3 L OGIC AND F AULT S IMULATION Jiun-Lang Huang National Taiwan University, Taipei, Taiwan James C.-M. Li National Taiwan University, Taipei, Taiwan Duncan M. (Hank) Walker Texas A&M University, College Station, Texas ABOUT THIS CHAPTER Simulation is a powerful set of techniques that are used heavily in digital circuit verification, test development, design debug, and diagnosis. During the design stage, logic simulation is performed to help verify whether the design meets its speci- fications and contains any design errors. It also helps locate these design errors that escape to fabrication during design debug. In test development, faulty circuit behavior is simulated with a set of test patterns to assess the pattern quality and guide further pattern development. Simulation of faulty circuits is referred to as fault simulation and is also used during fault diagnosis, where test results are used to locate manufacturing defects within the hardware.
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