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138_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

138_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 107 Specification Manual design or Via synthesis Circuit description Input stimuli Testbench development Logic simulation Simulated responses Response analysis Expected responses yes Bug? no Next design stage FIGURE 3.1 Logic simulation for design verification. The flow of using logic simulation for digital circuit design verification is shown in Figure 3.1. The functional specification documents the required functionality and performance for the target design. During each design stage, a corresponding circuit description that contains ESL code for the behavioral design, HDL code for the RTL design, a netlist for the gate-level design, or SPICE models for the switch- and transistor-level design is generated in conformance with the given specification. To ensure conformance, verification testbenches consisting of a set of input stimuli and expected output responses are created. The logic simulator then takes the circuit
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Unformatted text preview: description and the input stimuli as inputs and produces the simulated responses. Any discrepancy between the simulated and expected responses (detected by the response analysis process) indicates the existence of a design bug. The circuit is then redesigned or modified until no more design errors exist. The design process then advances to the next design stage. 3.1.2 Fault Simulation for Test and Diagnosis The major difference between logic simulation and fault simulation lies in the nature of the nonidealities they deal with. Logic simulation is intended for iden-tifying design errors using the given specifications or a known good design as the reference. Design errors may be introduced by human designers or EDA tools...
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