Logic and Fault Simulation109BALEFG3G2JKHG4CG1FIGURE 3.2The gate-level model of the combinational circuitN.3.2.1Gate-Level NetworkA gate-level network is described as the interconnections of logic gates, which arecircuit elements that realize Boolean operations or expressions. The available gatesto realize a Boolean expression range from the standard gates (AND, OR, NOT,NAND, and NOR) to complex gates such as XOR and XNOR. For example, thecombinational circuitN1in Figure 3.2 is composed of an OR gate (G1), an ANDgate (G2), an inverter (G3), and a NOR gate (G4). The Boolean expression associatedwith the network can be obtained after a few Boolean algebraic manipulations2:K=A·E+E=A+E=A·B+C220.127.116.11Sequential CircuitsMost logic designs aresequential circuits, which differ from combinationalcircuits in that their outputs depend on both the current and past input values; thatis, they have memories. Sequential circuits are divided into two categories: syn-chronous and asynchronous. Here, we limit our discussion to synchronous circuits
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