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140_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 140_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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Logic and Fault Simulation 109 B A L E F G 3 G 2 J K H G 4 C G 1 FIGURE 3.2 The gate-level model of the combinational circuit N . 3.2.1 Gate-Level Network A gate-level network is described as the interconnections of logic gates, which are circuit elements that realize Boolean operations or expressions. The available gates to realize a Boolean expression range from the standard gates (AND, OR, NOT, NAND, and NOR) to complex gates such as XOR and XNOR. For example, the combinational circuit N 1 in Figure 3.2 is composed of an OR gate ( G 1 ), an AND gate ( G 2 ), an inverter ( G 3 ), and a NOR gate ( G 4 ). The Boolean expression associated with the network can be obtained after a few Boolean algebraic manipulations 2 : K = A · E + E = A + E = A · B + C 3.2.1.1 Sequential Circuits Most logic designs are sequential circuits , which differ from combinational circuits in that their outputs depend on both the current and past input values; that is, they have memories. Sequential circuits are divided into two categories: syn- chronous and asynchronous. Here, we limit our discussion to synchronous circuits
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