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141_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 141_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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110 VLSI Test Principles and Architectures Combinational logic Y 1 z 1 z 2 z m Y 2 y l x n Y l y 2 y 1 x 1 x 2 Flip-flops Clock ± FIGURE 3.3 The Huffman model of a sequential circuit. the active clock transition the states of all the flip-flops are updated according to the PPO values at that time and the flip-flop characteristic functions ( e.g. , y i = Y i for a D flip-flop). In the gate-level description, a flip-flop may be modeled as a functional block or as the interconnections of logic gates. Figure 3.4 shows the NAND implementation of the positive-edge-triggered D flip-flop and its functional symbol. Besides data ( D ) and clock ( Clock ) inputs, the D flip-flop also has active low asynchronous preset ( PresetB ) and clear ( ClearB ) inputs. Its outputs are the uncomplemented ±Q² and complemented ( QB ) data. 3.2.2 Logic Symbols The basic mathematics for most digital systems is the two-valued Boolean algebra
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Unformatted text preview: (referred to as Boolean algebra hereafter for convenience). In Boolean algebra, a variable can assume only one of the two values, true or false , which are represented by the two symbols “1” and “0,” respectively. Note that “1” and “0” here do not represent numerical quantities. Physical representations of the two symbols depend on the logic family of choice. Consider the most popular CMOS logic as an example; the two symbols “1” and “0” represent two distinct voltage levels, V dd and ground, 3 respectively. Whether a signal’s value is 1 or 0 depends on which voltage source it is connected to. 4 3 Assume that positive logic is used. 4 In the following discussion, it is assumed that the CMOS logic family is chosen....
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