142_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

142_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Logic and Fault Simulation 111 DFF PresetB PresetB D D Q Q QB QB ClearB Clock Clock ClearB ± FIGURE 3.4 Positive-edge-triggered D flip-flop. In addition to 1 and 0, logic simulators often include two more symbols: u (unknown) and Z (high-impedance); the former represents the uncertain circuit behavior, and the latter helps resolve the behavior of tristate logic. For cases when 0, 1, u , and Z are insufficient to meet the required simulation accuracy, intermediate logic states that incorporate both value and strength may be utilized. 3.2.2.1 Unknown State u Almost all practical digital circuits contain memory elements ( e±g ., flip-flops and memories) to store the circuit state; however, when these circuits are powered up, the initial states of their memory elements are usually unknown. To handle such
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: situations, the logic symbol u is introduced to indicate an unknown logic value. By associating u with a signal, we mean that the signal is 1 or 0, but we are not sure which one is the actual value. Basic Boolean operations for ternary logic (0, 1, and u ) are straightforward. First, the three symbols are viewed as three sets of symbols: 0 as {0}, 1 as {1}, and u as {0, 1}. Then, the outcome of a ternary logic operation is the union of the results obtained by applying the same operation to the elements of the sets; for example, the result of 0 · u is derived as follows: · u = ² ³ · ² ´ 1 ³ = ² · ´ · 1 ³ = ² ´ ³ = ² ³ =...
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online