144_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

144_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 113 To resolve the problem of information loss, one would have to assign to each flip-flop a unique unknown symbol u i and associate with u i the following rules: NOT ±u i ² = u ± i NOT ±u ± i ² = u i u i · u ± i = 0 u i + u ± i = 1 Let us revisit the example in Figure 3.5. Based on the above rules, the output of G 3 will be u ± instead of u , and finally one has K = 0, the correct answer. The problem with this approach is that signals that are affected by multiple unknown symbols have to be expressed as Boolean expressions of u i ’s. As the number of unknown symbols grows, the required symbolic simulation becomes cumbersome. 3.2.2.2 High-Impedance State Z Until now, the logic signal states that we have discussed are 1 and 0, indicating that the signal is connected to either V dd or ground. (The unknown symbol indicates
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Unformatted text preview: uncertainty; however, the signal of interest is still 1 or 0.) In addition to 1 or 0, tristate gates have a third, high-impedance state, denoted by logic symbol Z . Tristate gates permit several gates to time-share a common wire, called a bus . A signal is in the Z state if it is connected to neither V dd nor ground. Figure 3.6 depicts a typical bus application. In this example, three bus drivers ( G 1 , G 2 , and G 3 ) drive the bus wire y . Each driver G i is controlled by an enable signal e i , and its output o i is determined as follows: o i = ± x i if e i = 1 Z if e i = pull-up or down DFF e 1 G 1 G 2 G 3 e 2 x 1 o 1 o 2 o 3 x 2 x 3 e 3 y Resolution Function ± FIGURE 3.6 Tristate circuits....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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