147_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

147_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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116 VLSI Test Principles and Architectures Start return c' i return c i return u u_in false u_in is true? u_in true v next input next input? ν == u ? v == c ? yes yes yes yes no no no no FIGURE 3.7 The input scanning algorithm. The input scanning algorithm flow is depicted in Figure 3.7. The scanning process (the shaded region) detects the existence of controlling and unknown inputs. If an unknown input is encountered, the u_in variable is set to true. On the other hand, once a controlling input is detected, the algorithm will exit the loop and return c i . If there is no controlling input, the output value depends on whether there is any unknown input. 3.2.3.3 Input Counting Examining the input scanning algorithm, one can observe that knowing the number of controlling and unknown inputs is sufficient to evaluate the output of AND, OR, NAND, and NOR gates. Based on this observation, the input counting algorithm maintains, for each gate, the number of controlling and unknown inputs, denoted
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Unformatted text preview: by c_count and u_count , respectively. During logic simulation, the two counts are updated if the value of any gate input changes. Consider the NAND gate as an example. If one of its inputs switches from 0 to u , then c_count will be decremented and u_count incremented. Finally, the same rules as those for the input scanning algorithm are applied to determine the output value. 3.2.3.4 Parallel Gate Evaluation One way to speed up logic simulation is to implement simulation concurrency on the host computer. Because modern computers process data in the unit of a word, usually 32- or 64-bits wide, one can store in a single word multiple copies of a signal (with respect to different input vectors) and process them at the same time. This is referred to as parallel simulation or bitwise parallel simulation ....
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