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Unformatted text preview: by c_count and u_count , respectively. During logic simulation, the two counts are updated if the value of any gate input changes. Consider the NAND gate as an example. If one of its inputs switches from 0 to u , then c_count will be decremented and u_count incremented. Finally, the same rules as those for the input scanning algorithm are applied to determine the output value. 22.214.171.124 Parallel Gate Evaluation One way to speed up logic simulation is to implement simulation concurrency on the host computer. Because modern computers process data in the unit of a word, usually 32- or 64-bits wide, one can store in a single word multiple copies of a signal (with respect to different input vectors) and process them at the same time. This is referred to as parallel simulation or bitwise parallel simulation ....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
- Spring '08