Logic and Fault Simulation1171ABCEJHKG4G1G2G3001111000101110000101101000FIGURE 3.8Parallel gate evaluation.Figure 3.8 depicts how parallel simulation is realized to simulate circuitNwithbinary logic on a computer with a 4-bit word. Because one bit is sufficient tocode binary logic symbols, four vectors can be stored in a word and processedin parallel. In this example, the four input vectors to be simulated areABC=110 , 010 , 011 , 100, and next to each signal is the 4-bit data word that storesthe values corresponding to the four input vectors. Bitwise logic operations areperformed to evaluate the gate outputs.Parallel simulation is more complicated for multi-valued logic. Consider theternary logic for which two bits are needed to code the three symbols. One possiblecoding scheme is:v0=00v1=11vu=01Assume that the word width of the host computer is
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