148_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

148_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 117 1 A B C EJ H K G 4 G 1 G 2 G 3 001 1110 0010 0001 0110 1000 ± FIGURE 3.8 Parallel gate evaluation. Figure 3.8 depicts how parallel simulation is realized to simulate circuit N with binary logic on a computer with a 4-bit word. Because one bit is sufficient to code binary logic symbols, four vectors can be stored in a word and processed in parallel. In this example, the four input vectors to be simulated are ABC = ±² 110 ³ , ² 010 ³ , ² 011 ³ , ² 100 ³´ , and next to each signal is the 4-bit data word that stores the values corresponding to the four input vectors. Bitwise logic operations are performed to evaluate the gate outputs. Parallel simulation is more complicated for multi-valued logic. Consider the ternary logic for which two bits are needed to code the three symbols. One possible coding scheme is: v 0 = ² 00 ³ v 1 = ² 11 ³ v u = ² 01 ³ Assume that the word width of the host computer is
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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