148_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Logic and Fault Simulation 117
1
A
B
C
E J
H
K G
4
G
1
G
2
G
3
0 0 1
1 1 1 0
0 0 1 0
1 1 1 0 0 0 0 1
0 1 1 0
1 0 0 0
FIGURE 3.8
Parallel gate evaluation.
Figure 3.8 depicts how parallel simulation is realized to simulate circuit N with
binary logic on a computer with a 4-bit word. Because one bit is sufficient to
code binary logic symbols, four vectors can be stored in a word and processed
in parallel. In this example, the four input vectors to be simulated are ABC =
110 , 010 , 011 , 100 , and next to each signal is the 4-bit data word that stores
the values corresponding to the four input vectors. Bitwise logic operations are
performed to evaluate the gate outputs.
Parallel simulation is more complicated for multi-valued logic. Consider the
ternary logic for which two bits are needed to code the three symbols. One possible
coding scheme is:
v
0
= 00
v
1
= 11
v
u
= 01
Assume that the word width of the host computer is