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118 VLSI Test Principles and Architectures 3.2.4 Timing Models Delay is a fact of life for all electrical components, including logic gates and inter- connection wires. In this section, we discuss the commonly used gate and wire delay models. Transport Delay The transport delay refers to the time duration it takes for the effect of gate input changes to appear at gate outputs. Several transport delay models characterize this phenomenon from different aspects. The nominal delay model specifies the same delay value for the output rising and falling transitions and thus is also referred to as the transition-independent delay model. Consider the AND gate G in Figure 3.9 as an example. Here B is fixed at 1; thus, the output of G is only affected by A . Assuming that G has a nominal delay of d N = 2 ns and A is pulsed to 1 for 1 ns, the corresponding simulation result is shown in Figure 3.9a. Using the nominal delay model, the output waveform at F is simply a version of
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Unformatted text preview: A delayed by 2 ns. For cases where the rising and falling times are different ( e.g. , the pull-up and pull-down transistors of the gate have different driving strengths), one may opt for the rise/fall delay model. In Figure 3.9b, the setup is the same as that in Figure 3.9a, except that the rise/fall delay model is employed instead; the rise and fall delays are d r = 2 ns and d f = 1 ± 5 ns, respectively. Due to the difference between the two delays, the duration of the output pulse shrinks from 1 to 0.5 ns. If the gate transport delay cannot be uniquely determined ( e.g. , due to process variations), one may employ the min–max delay model. In the min–max delay (a) Nominal delay (b) Rise/fall delay (c) Min–Max delay A F G B = 1 d N = 2 ns d r = 2 ns d min = 1 ns d max = 2 ns d f = 1.5 ns A F A F A F 1 1 1 1.5 1.5 1 2 2 2 2 2 ± FIGURE 3.9 Transport delay models....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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