Unformatted text preview: delay of 1.5 ns and a nominal delay of 3 ns. Let us fix B at 1 and apply a pulse on A . In Figure 3.10a, the 1-ns pulse is filtered and the output remains at a constant 0. In Figure 3.10b, the pulse is long enough (2 ns) and an output pulse is observed 3 ns later. 22.214.171.124 Wire Delay In the past, when gate delays dominated circuit delay, the interconnection wires were regarded as ideal conductors with no signal propagation delay. In reality, wires are three-dimensional structures that are inherently resistive and capacitive. Furthermore, they may interact with neighboring conductors to form mutual capac-itance. Figure 3.11a illustrates the distributed RLC model of a metal wire. In the (a) Pulse duration less than d I (b) Pulse duration longer than d I A F G B = 1 d I = 1.5 ns d N = 3 ns A F 1 A F 2 2 3 3 ± FIGURE 3.10 Inertial delay....
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- Spring '08
- Gate, Logic gate, Wire, Delay calculation, propagation delay, fault simulation, inertial delay