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150_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 150_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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Logic and Fault Simulation 119 model, the minimum and maximum gate delays ( d min and d max ) are specified to represent the ambiguous time interval in which the output change may occur. In Figure 3.9c, the minimum and maximum delays are 1 and 2 ns, respectively, and a 1.5-ns pulse is applied at A . In response to the delay uncertainty, two ambiguous intervals (the shaded regions), corresponding to the rising and falling transitions, are observed at output F . Within the two ambiguous intervals, the exact output value is unknown. Note that one may combine the min–max and rise/fall delay models to represent more complicated delay behaviors. 3.2.4.2 Inertial Delay The inertial delay is defined as the minimum input pulse duration necessary for the output to switch states. Pulses shorter than the inertial delay cannot pass through the circuit element. The inertial delay models the limited bandwidth of logic gates. Figure 3.10 illustrates this filtering effect. Assume that the AND gate has an inertial
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Unformatted text preview: delay of 1.5 ns and a nominal delay of 3 ns. Let us fix B at 1 and apply a pulse on A . In Figure 3.10a, the 1-ns pulse is filtered and the output remains at a constant 0. In Figure 3.10b, the pulse is long enough (2 ns) and an output pulse is observed 3 ns later. 3.2.4.3 Wire Delay In the past, when gate delays dominated circuit delay, the interconnection wires were regarded as ideal conductors with no signal propagation delay. In reality, wires are three-dimensional structures that are inherently resistive and capacitive. Furthermore, they may interact with neighboring conductors to form mutual capac-itance. Figure 3.11a illustrates the distributed RLC model of a metal wire. In the (a) Pulse duration less than d I (b) Pulse duration longer than d I A F G B = 1 d I = 1.5 ns d N = 3 ns A F 1 A F 2 2 3 3 ± FIGURE 3.10 Inertial delay....
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