151_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

151_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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120 VLSI Test Principles and Architectures (a) Distributed wire delay model (b) Fanout delay modeling b a c d d a–b d a–c d a–d p q ± FIGURE 3.11 Wire delay model. presence of the passive components, it takes finite time, called the propagation delay , for a signal to travel from point p to point q . In general, wire delays are specified for each connected gate output and gate input pair because the physical distances and thus the propagation delays between the driver and receiver gates vary. In Figure 3.11b, the inverter output a branches out to drive three gates. To model the wire delays associated with the three signal paths, one may insert delay elements d a b , d a c , and d a d into the fanout branches. For convenience, wire delays may also be viewed as the receiver gate input delays and become part of the receiver gate delay model. Thanks to the advance of integrated-circuit fabrication technology, continuous
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Unformatted text preview: device scaling has significantly reduced gate delays; however, wire delays do not benefit as much from device scaling. As a result, wire delays have replaced gate delays as the dominant performance-limiting factor. The challenge of wire delay modeling is that accurate delay values are not available until the physical design stage when the functional blocks are placed and signal nets are routed. Very often, the designers have to go back to earlier design stages to fix the timing violations, a time-consuming process. 3.2.4.4 Functional Element Delay Model Functional elements, such as flip-flops, have more complicated behaviors than simple logic gates and require more sophisticated timing models. In Table 3.3, the I/O delay model of the positive-edge-triggered D flip-flop (Figure 3.4) is depicted....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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