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Unformatted text preview: device scaling has significantly reduced gate delays; however, wire delays do not benefit as much from device scaling. As a result, wire delays have replaced gate delays as the dominant performance-limiting factor. The challenge of wire delay modeling is that accurate delay values are not available until the physical design stage when the functional blocks are placed and signal nets are routed. Very often, the designers have to go back to earlier design stages to fix the timing violations, a time-consuming process. 188.8.131.52 Functional Element Delay Model Functional elements, such as flip-flops, have more complicated behaviors than simple logic gates and require more sophisticated timing models. In Table 3.3, the I/O delay model of the positive-edge-triggered D flip-flop (Figure 3.4) is depicted....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
- Spring '08