Logic and Fault Simulation121TABLE 3.3±The D Flip-Flop I/O Delay ModelInput ConditionPresent StateOutputsDelays (ns)CommentsDClockPresetBClearBqQQBtoQtoQBXX↓10↑↓1.61.8Asynchronous preset1↓1↓↑1.81.6Asynchronous clear1↑11023Q±0→10↑1321→0Note:Xindicates “don’t care.’’Take the asynchronous preset operations (second row) as an example. Regardlessof theClockandDvalues, if the current flip-flop state (q)is0andClearBremains1, changingPresetBfrom 1 to 0 (denoted by the down arrow) will cause outputtransitions atQandQBafter 1.6 and 1.8 ns, respectively. Besides the input-to-outputtransport delay, the flip-flop timing model usually contains timing constraints, suchas setup/hold times and inertial delays for each input.3.3LOGIC SIMULATIONIn this section, we will discuss two commonly used gate-level logic simulationmethodologies: compiled-code and event-driven. The reader should note that,
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