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Logic and Fault Simulation 121 TABLE 3.3 ± The D Flip-Flop I/O Delay Model Input Condition Present State Outputs Delays (ns) Comments D Clock PresetB ClearB q QQ B to Q to QB XX 1 0 ↑↓ 1.6 1.8 Asynchronous preset 1 1 ↓↑ 1.8 1.6 Asynchronous clear 1 11 0 23 0 1 0 1 32 1 0 Note : X indicates “don’t care.’’ Take the asynchronous preset operations (second row) as an example. Regardless of the Clock and D values, if the current flip-flop state ( q )is0and ClearB remains 1, changing PresetB from 1 to 0 (denoted by the down arrow) will cause output transitions at Q and QB after 1.6 and 1.8 ns, respectively. Besides the input-to-output transport delay, the flip-flop timing model usually contains timing constraints, such as setup/hold times and inertial delays for each input. 3.3 LOGIC SIMULATION In this section, we will discuss two commonly used gate-level logic simulation methodologies: compiled-code and event-driven. The reader should note that,
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