Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
122 VLSI Test Principles and Architectures gate level description logic optimization logic levelization code generation compiled code (b) Code generation flow start end no yes next vector? read in next input vector v output simulation results run compiled code with input v in host machine (a) Simulation flow ± FIGURE 3.12 Compiled code simulation. before optimization after optimization
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: A A A A A A A B (a) (b) (c) (d) (e) A B 1 A 1 ± FIGURE 3.13 Logic optimization. 4. Replace three consecutive inverters with a single one (Figure 3.13d); this case is common in clock trees. 5. Replace a buffer with a single wire (Figure 3.13e). 6. Remove logic gates that drive unobservable or floating outputs....
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online