154_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 154_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - queue...

This preview shows page 1. Sign up to view the full content.

Logic and Fault Simulation 123 Because each gate corresponds to one or more statements in the compiled code, logic optimization reduces the program size and execution time. 3.3.1.2 Logic Levelization To avoid unnecessary computations, logic gates must be evaluated in an order such that a gate will not be evaluated until all its driving gates have been evaluated. For circuit N , the evaluation order: G 1 G 2 G 3 G 4 satisfies this requirement. For most networks, there exists more than one evaluation order that meets the requirement; for example, for N : G 1 G 3 G 2 G 4 The logic levelization algorithm shown in Figure 3.14 can be utilized to produce the desired gate evaluation order. At the beginning of the algorithm, all the PIs are assigned level 0, and all the PI fanout gates are appended to the first-in/first-out
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: queue Q that stores the gates to be processed. While Q is non-empty, the first gate g in Q is popped out. If all the driving gates of g are levelized and the maximum level is l , g is assigned level l + 1 and all of the fanout gates of g are appended to Q ; otherwise, g is put back in Q to be processed later. The levelization process repeats until Q is empty. Note that for gates assigned the same level, their order start assign level 0 to all PI ′ s put all PI fanout gates in Q Q empty? end yes yes no no append g to Q ready to levelize g ? pop next gate g from Q append g ′ s fanout gates to Q 1. l = maximum of g ′ s driving gate levels 2. assign l + 1 to g ± FIGURE 3.14 The logic levelization algorithm....
View Full Document

## This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online