124VLSI Test Principles and ArchitecturesTABLE 3.4±The Levilization Process of Circuit NStepABCG1G2G3G4Q0000<G2,G1>11,G2>212,G3>3123,G4>41224>50001223<>of evaluation does not matter. This levelization process is also referred to asrankordering.The levelization process for circuitNis shown step by step in Table 3.4. At thebeginning, PIs are assigned level 0, and their fanout gatesG1andG2are appendedtoQ. In step 1,G2is not ready and put back toQbecauseG1is not levelized yet.In step 2,G1is assigned level 1 because it is driven by level 0 PIs only. At the endof the process, the following orders are produced:G1→G2→G3→G4G1→G3→G2→G126.96.36.199Code GenerationDepending on performance, portability, and maintainability needs, different codegeneration techniques may be used [Wang 1987]. Three approaches for code gen-eration are described below:±Approach 1—High-level programming language source code. The net-work to be simulated is described in a high-level programming language,such as C. The advantage is that it is easier to debug and can be ported to
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