155_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

155_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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124 VLSI Test Principles and Architectures TABLE 3.4 ± The Levilization Process of Circuit N Step ABCG 1 G 2 G 3 G 4 Q 0 000 <G 2 , G 1 > 1 1 , G 2 > 2 1 2 , G 3 > 3 1 2 3 , G 4 > 4 1 2 2 4 > 5 0 0 01223 <> of evaluation does not matter. This levelization process is also referred to as rank ordering . The levelization process for circuit N is shown step by step in Table 3.4. At the beginning, PIs are assigned level 0, and their fanout gates G 1 and G 2 are appended to Q . In step 1, G 2 is not ready and put back to Q because G 1 is not levelized yet. In step 2, G 1 is assigned level 1 because it is driven by level 0 PIs only. At the end of the process, the following orders are produced: G 1 G 2 G 3 G 4 G 1 G 3 G 2 G 4 3.3.1.3 Code Generation Depending on performance, portability, and maintainability needs, different code generation techniques may be used [Wang 1987]. Three approaches for code gen- eration are described below: ± Approach 1 High-level programming language source code . The net- work to be simulated is described in a high-level programming language, such as C. The advantage is that it is easier to debug and can be ported to
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