156_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

156_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 125 Shown below is the pseudo code for circuit N . In the actual implementation, each statement is replaced with the corresponding language constructs or machine instructions, depending on the adopted code generation approach: while(true) do read( A, B, C ); E OR( B, C ); H AND( A, E ); J NOT( E ); K NOR( H, J ); end Compiled-code simulation is most effective when binary logic simulation suffices. In such cases, machine instructions are readily available for Boolean operations ( e.g. , AND, OR, and NOT). Its main limitations include its incapability of timing modeling and low simulation efficiency. The compiled-code simulation methodology cannot handle gate and wire delay models. As a result, it fails to detect timing problems such as glitches and race conditions. The low efficiency of compiled-code simulation is because the entire network is evaluated for each input vector, despite the fact that in general only 1 to 10% of input signals change values between consecutive vectors. 3.3.2
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