158_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

158_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Logic and Fault Simulation 127 t 0 t 1 t i p, v p + q, v q + w, v w + s, v s + r, v r + ± FIGURE 3.17 Priority queue event scheduler. example, in Figure 3.17, the value of signal w will switch to v + w at t i .If t i is not in the time stamp list yet, the scheduler will first place it in the list according to the chronological order. For the priority queue scheduler in Figure 3.17, the time needed to locate a time stamp to insert an event grows with the circuit size. To improve the event scheduler efficiency, one may use, instead of a linked list, an array of evenly spaced time stamps. Although some entries in the array may have empty event lists, the overall search time is reduced because the target time stamp can be indexed by its value. Further enhancement is possible with the concept of timing wheel [Ulrich 1969]. Let the time resolution be one time unit and the array size M . A time stamp that is d time units ahead of current simulation time (with array index i ) is stored in the array and indexed by (
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.
Ask a homework question - tutors are online