159_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

159_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - G...

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128 VLSI Test Principles and Architectures start end next time stamp? get next time stamp t retrieve current event list L E no no no no yes yes yes yes L E empty? L A empty? get next gate g from L A get next event ( g, v g ) from L E 1. v g v g 2. append g s fanout gates to activity list L A evaluate g and schedule ( g,v g ) at t + delay( g ) + + + v g == v g ? + ± FIGURE 3.18 Two-pass event-driven simulation strategy. In the following, we will use circuit N to demonstrate the two-pass event-driven strategy. In this example, the nominal delays for
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Unformatted text preview: G 1 , G 2 , G 3 , and G 4 are 8, 8, 4, and 6 ns, respectively, and there are four input events (see Figure 3.19): ( A , 1, 0), ( C , 0, 2), ( B , 0, 4), and ( A , 0, 8), where the notation ( w , v ± w , t ) represents the event that signal w switches to v ± w at time t . The simulation progress is shown in Table 3.5. A B C E H J K 2 4 6 8 10 12 14 16 18 20 22 ± FIGURE 3.19 Flow of events and voided events....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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