160_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 160_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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Logic and Fault Simulation 129 TABLE 3.5 ± Two-Pass Event-Driven Simulation Time L E L A Scheduled Events 0 {( A , 1)} { G 2 } {( H ,1 ,8)} 2 {( C , 0)} { G 1 } {( E , 1, 10)} 4 {( B , 0)} { G 1 } {( E , 0, 12)} 8 {( A , 0), ( H , 1)} { G 2 , G 4 } {( H , 0, 16), ( K , 0, 14)} 10 {( E , 1)} 12 {( E , 0)} { G 2 , G 3 } {( H , 0, 20), ( J , 1, 16)} 14 {( K , 0)} 16 {( H , 0), ( J , 1)} { G 4 } {( K , 0, 22)} 20 {( H , 0)} 22 {( K , 0)} At time 0, there is only one primary input event ( A , 1). Because A drives G 2 , G 2 is added to activity list L A . Evaluation of G 2 returns H = 1; therefore, the event ( H , 1) is scheduled at time 8 ( i±e± , 8 ns, the delay of G 2 after the current time.) At time stamps 2 and 4, the two input events at C and B are processed in the same way. There are two events at time 8: the input event ( A , 0) and the scheduled event ( H , 1) from time stamp 0. As both events are valid, the two affected gates, G 2 and G 4 , are put in L A
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## This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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