161_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 161_pdfsam_VLSI - static hazard refers to the transient pulse on a signal line whose static value does not change Depending on what the signal’s

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130 VLSI Test Principles and Architectures 3.3.4 Hazards Because of the difference in delays along reconvergent signal paths, input transi- tions may cause unwanted transient pulses or glitches, called hazards , to appear at internal signals or primary outputs. We will use circuit N to illustrate the cause of hazards. In this example, the inverter has a nominal delay of 3 ns, and the other gates have nominal delays of 2 ns. At first, the input vector to circuit N is ABC = 110 and the output value is K = 0. After circuit N stabilizes, the second input vector ABC = 100 is applied. Without considering the gate delays, the simulator will report that K remains unchanged; however, as shown in Figure 3.20, a delay-aware simu- lator will reveal the existence of a spurious one pulse at K , called a static 0-hazard. Hazards are divided into two categories: static and dynamic. A
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Unformatted text preview: static hazard refers to the transient pulse on a signal line whose static value does not change. Depending on what the signal’s static value is, a static hazard may be a static 1-hazard or a static 0-hazard . A dynamic hazard , on the other hand, refers to the transient pulse during a 0-to-1 or 1-to-0 transition. Figure 3.21 illustrates the possible outputs of a network with hazards. In the figures, only one hazard pulse is shown, but in general there can be multiple pulses. The presence of hazards may cause a sequential network to malfunction. Following the above example, if the A B C E H J K 1 2 3 4 5 6 7 8 ± FIGURE 3.20 Static 0-hazard. static 1-hazard static 0-hazard dynamic 1-hazard dynamic 0-hazard ± FIGURE 3.21 Types of hazards....
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## This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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