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162_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

162_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 131 output signal K is connected to the active high clear input of a flip-flop, the flip-flop may be erroneously cleared by the 1 spike. Hazard detection is straightforward if the network timing information is avail- able and supported by the simulator; however, the accuracy of this approach suffers from gate delay deviations caused by process variations. In the following, we dis- cuss multivalued logic-based hazard detection techniques that perform worst-case hazard analysis regardless of the timing model. 3.3.4.1 Static Hazard Detection Recall that hazards are caused by the difference of delays associated with recon- vergent paths ( e.g. , E H K and E J K in circuit N ). (The event flow corresponding to the two paths are shown in Figure 3.20.) One must therefore ana- lyze the transient behavior of the network for hazard detection; however, without the correct delay information, it is impossible to predict the exact moment at which a signal transition occurs. One solution to this difficulty is to model the network’s
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