163_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

163_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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132 VLSI Test Principles and Architectures TABLE 3.6 ± Multivalued Logic for Hazard Detection Symbol Interpretation Six-Valued Logic Eight-Valued Logic 0 Static 0 {000} {0000} 1 Static 1 {111} {1111} R Rise transition ± 001,011 ² = 0 u 1 {0001,0011,0111} F Fall transition ± 100,110 ² = 1 u 0 {1110,1100,1000} 0* Static 0-hazard ± 000,010 ² = 0 u 0 {0000,0100,0010,0110} 1* Static 1-hazard ± 111,101 ² = 1 u 1 {1111,1011,1101,1001} R* Dynamic 1-hazard {0001,0011,0101,0111} F* Dynamic 0-hazard {1000,1010,1100,1110} 3.3.4.2 Dynamic Hazard Detection A dynamic hazard causes an unwanted pulse to appear during a 0-to-1 or 1-to-0 transition. To detect dynamic hazards, four-bit sequences are necessary. The eight- valued logic [Hayes 1986] that covers all the 4-bit sequences necessary for dynamic hazard detection is shown in Table 3.6. Compared to six-valued logic, two symbols R* and F* are added to denote the dynamic 1- and 0-hazard, respectively. The result of a Boolean operation on the eight-valued logic symbols is the union of the results
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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