164_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

164_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 133 terms “test vectors” and “test patterns” are interchangeable in most cases, for the subject of logic simulation the term “test vectors” is preferred, because test vectors are mostly written by human designers for design verification. For fault simulation, on the other hand, the term “test patterns” is used, as the fault simulators frequently work with ATPG to grade test patterns. 3.4.1 Serial Fault Simulation Serial fault simulation is the simplest fault simulation technique. It consists of fault- free and faulty circuit simulations. Initially, fault-free logic simulation is performed on the original circuit to obtain the fault-free output responses. The fault-free responses are stored and later employed to determine whether a test pattern can detect a fault or not. After fault-free simulation, a serial fault simulator simulates faults one at a time. For each fault, fault injection is first performed, which mod- ifies the original circuit to mimic the circuit behavior in the presence of the fault.
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