165_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

165_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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134 VLSI Test Principles and Architectures TABLE 3.7 ± Serial Fault Simulation Results for Figure 3.22 Input Internal Output Pattern No. A B C E F L J H K good K f K g P 1 0 1 0 1 1 1 0 0 1 0 1 P 2 0 0 1 1 1 1 0 0 1 0 1 P 3 1 0 0 0 0 0 1 0 0 0 1 performed to obtain the faulty outputs K g = ± 1,1, 1 ² (also listed in Table 3.7). Fault g is detected by pattern P 3 but not P 1 and P 2 . In this example, nine simulation runs are performed: three fault-free and six faulty circuit simulations. These nine simulation runs can be divided into three simulation passes . In each simulation pass, either the fault-free or the faulty circuit is simulated for the whole test pattern set; thus, the first simulation pass consists of fault-free simulations for P 1 , P 2 , and P 3 , and the second and third passes correspond to the faulty circuit simulations of faults f and g , respectively, for P 1 , P 2 , and P 3 . By careful inspection of the simulation results in Table 3.7, one can observe that, if we are only concerned with the set of faults that is detected by the test set
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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