166_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

166_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 135 start F collapsed fault list 1. get next fault f from F 2. reset pattern counter 1. get next fault p 2. fault simulation for pattern p end next fault? no fault-free simulation for all patterns next pattern? no no mismatch? delete f from F yes yes yes ± FIGURE 3.23 The serial fault simulation algorithm flow. 3.4.2 Parallel Fault Simulation Similar to parallel logic simulation, fault simulation can take advantage of the bitwise parallelism inherent in the host computer to reduce fault simulation time. For example, in a 32-bit wide CPU, logic operations (AND, OR, or XOR) can be
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Unformatted text preview: performed on all 32 bits at once. There are two ways to realize bitwise parallelism in fault simulation: parallelism in faults and parallelism in patterns. These two approaches are referred to as parallel fault simulation and parallel pattern fault simulation . 3.4.2.1 Parallel Fault Simulation Parallel fault simulation was proposed as early as the 1960s [Seshu 1965]. Assuming that binary logic is utilized, one bit is sufficient to store the logic value of a signal....
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