167_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

167_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
136 VLSI Test Principles and Architectures Thus, in a host computer using w -bit wide data words, each signal is associated with a data word of which w 1 bits are allocated for w 1 faulty circuits and the remaining bit is reserved for the fault-free circuit. This way, w 1 faulty and one fault-free circuit can be processed in parallel using bitwise logic operations which correspond to a speedup factor of approximately w 1 compared to serial fault simulation. A fault is detected if its bit value differs from that of the fault-free circuit at any of the outputs. We will reuse the example from serial fault simulation to illustrate the parallel fault simulation process. Assuming that the width of a computer word is three bits, the first bit stores the fault-free (FF) circuit response, and the second and third bits store the faulty responses in the presence of faults f and g , respectively. The simulation results are shown in Table 3.8. Because fault f , A stuck-at one, uses the second bit, it is injected by forcing the second bit of the data word of signal
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online