168_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

168_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Logic and Fault Simulation 137 A f G f G g J g G 1 G 3 G 4 G 2 A B C E F L J K H 010 110 ± FIGURE 3.24 Fault injection for parallel fault simulation. inserted. To force the second bit of A f to one without affecting the other two bits, the side input of G f is set to be 010. Note that the injection of fault f does not affect the fault-free circuit and the faulty circuit with fault g . Similarly, injecting fault g ,a stuck-at zero fault, is achieved by adding the AND gate G g and setting its side input to be 110. Note that the parallel fault simulation technique is applicable to the unit or zero delay models only. More complicated delay models cannot be modeled because several faults are evaluated at the same time. Furthermore, a simulation pass cannot terminate unless all the faults in this pass are detected. For example, we cannot drop fault f alone after simulating pattern P 1 because fault g is not detected yet. Parallel fault simulation is best used for simulating the beginning of the test pattern
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online