169_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

169_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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138 VLSI Test Principles and Architectures TABLE 3.9 ± PPSFP for Figure 3.22 In PPSFP, faults are injected by activating rising or falling events, depending on the stuck-at value, at the faulty signal. Thus, fault f , A stuck-at one, is injected by activating two rising events on input A . The faulty responses are { 0 , 0 , 0} which indicates that fault f is detected by the first and second patterns but not the third one. After fault f is simulated, fault f is removed by activating two falling events on input A at patterns P 1 and P 2 . Then, fault g is injected by activating one falling event on signal J at pattern P 3 . Three simulation runs are carried out. Figure 3.25 illustrates the simplified PPSFP flow. Again, fault collapsing is first executed to obtain the collapsed fault list F . Then, the first w patterns are simulated on the fault free circuit in parallel and the good outputs ( O good ) are stored. Then, each fault f in fault list F is simulated one by one using the same w test patterns. A fault is dropped and not simulated against the remaining test patterns if its
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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