170_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

170_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 139 F collapsed fault list F empty? next w patterns? next fault? get next fault f from F 1. apply next w patterns 2. O good good circuit outputs 1. remove last fault 2. inject fault f delete f from F end end yes yes yes yes no no no no start O f faulty circuit outputs of w patterns O f == O good ? ± FIGURE 3.25 The PPSFP flowchart. 3.4.3 Deductive Fault Simulation Deductive fault simulation [Armstrong 1972], unlike the fault simulation techniques described above, takes a very different approach; it is based on logic reasoning rather than simulation. For a given test pattern, deductive simulation identifies, all at once, the faults that can be detected. Deductive fault simulation can be very fast
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Unformatted text preview: because only fault-free simulations have to be performed. In deductive fault simulation, a fault list ( L x ) is associated with a signal x . L x is the set of faults that causes x to differ from its fault-free value. Figure 3.26 shows the fault list of each signal with respect to test pattern P 1 . Fault A/ 1 appears in L A because its presence causes the value of primary input A to deviate from its correct value of zero. Fault A/ 0 is not in the fault list because the value of A remains correct when the fault A /0 is present. The fault lists for inputs B and C are derived in the...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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