171_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 171_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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140 VLSI Test Principles and Architectures A B C EF L H K J L A = { A /1} L B = { B /0} L C = { C /1} 0 0 0 0 1 1 1 1 1 G 1 G 3 G 2 G 4 { B /0 , E /0}{ B /0 , E /0, F /0} { B /0 , E /0, F /0, J /1} { A /1, H /1, B /0 , E /0, F /0, J /1, K /0} { B /0 , E /0, L /0} { A /1, H /1} ± FIGURE 3.26 Deductive fault simulation ( P 1 ). same way. Based on logic reasoning, the process of deriving the fault list of a gate output from those of the gate inputs is called fault list propagation ; for example, the fault list of gate output E is the union of the fault list of B and the E/ 0 fault. Clearly, the E/ 0 fault should be included in L E as the correct value of E is one. On the other hand, because the fault-free value of C is a noncontrolling value of G 1 , the fault effect of each fault in L B will propagate to E (which causes E to be 1); therefore, all faults in L B are propagated to L E . L C is not propagated to the gate output because the other input B holds the controlling value (one) of gate G 1 . Similarly, the fault list L E is propagated to signals L and F . The fanout branches
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## This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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