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172_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 172_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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Logic and Fault Simulation 141 G 1 L B = { B /1} G 4 G 2 G 3 A B C E { C /0} F { C /0} L J { C /0} H K 0 0 1 1 1 L C = { C /0} 1 1 0 0 { C /0} { C /0} FIGURE 3.27 Deductive fault simulation ( P 2 ). G 1 L C = { C /1} L B = { B /1} L A = { A /0} G 4 G 2 G 3 A B C E { B /1, C /1, E /1} F { B /1, C /1, E /1, F /1} L { B /1, C /1, E /1, L /1} J { B /1, C /1, E /1, F /0, J /0} H K 1 0 0 0 0 0 1 0 0 { B /1, C /1, E /1, L /1} { F /1, J /0, K /1} FIGURE 3.28 Deductive fault simulation ( P 3 ). Although in our simple example, the fault list propagation rules are demonstrated only for two-input gates, they can be generalized to multiple input gates. Let I and z be the set of gate inputs and the gate output, respectively. Equation 3.1 shows the fault list propagation rule when all gate inputs hold noncontrolling values: L z = j I L j z/ c i (3.1) In Equation 3.1, c and i are the controlling and inversion values of the gate. (See Table 3.2 for the c and i values of basic gates.) Because no controlling value appears
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