173_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

173_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - S )...

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142 VLSI Test Principles and Architectures start end end F collapsed fault list no no yes yes next pattern? apply next pattern delete detected faults from F F empty? 1. fault-free simulation 2. propagate fault list ± FIGURE 3.29 Deductive fault simulation flowchart. gate inputs that hold the controlling and noncontrolling values, respectively, and the minus sign represents the set difference operation: L z = ±² ³ j S L j ´ ² µ j I S L j ´¶ · ±z/c i ± ² (3.2) The term ² ³ j S L j ´ ² µ j I S L j ´ represents the set of faults in the gate input fault lists that will propagate to the gate output. First, a fault cannot be observed unless it appears in every fault list of gate inputs in S , represented by the term ³ j S L j ; otherwise, some gate inputs will retain the controlling value and block the fault effect propagation. Second, the fault lists of the noncontrolling gate inputs ( i³e³ , I
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Unformatted text preview: S ) cannot propagate to the gate output, represented by the µ j ∈ I − S L j term and the set difference operation, because these faults prevent the gate output from being changed. Applying Equation 3.2 to the NOR gate G 4 in Figure 3.28, one has L K = ´L J − L H µ ∪ ±K/ 1 ² ; the faults in L H are taken out of L J because flipping H does not change the value of output K . Although deductive fault simulation is efficient in that it processes all faults at the same time, it has several limitations. The first problem is that unknown values are not easily handled. For each unknown value, both cases must be considered ( i³e³ , when the unknown is a controlling or noncontrolling value). The logic rea-soning becomes even more complicated if more than one unknown appears. See...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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