174_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

174_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 143 [Abramovici 1994] for more detailed discussions of this problem. The second prob- lem is that deductive fault simulation is only suitable for the zero-delay timing model, because no timing information is considered during the deductive fault propagation process. Finally, deductive fault simulation has a potential memory management problem. Because the size of fault lists cannot be predicted in advance, there can be a large variation in memory requirements during algorithm execution. 3.4.4 Concurrent Fault Simulation Because a fault only affects the logic in the fanout cone from the fault site, the good circuit and faulty circuits typically only differ in a small region. Concur- rent fault simulation exploits this fact and simulates only the differential parts of the whole circuit [Ulrich 1974]. Concurrent fault simulation is essentially an event-driven simulation with the fault-free circuit and faulty circuits simulated altogether.
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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