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175_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 175_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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144 VLSI Test Principles and Architectures fault lists with bad gates in gray are drawn beside the good gates. The fault indices are labeled in the middle of bad gates and their associated bad gate I/O values are labeled beside their I/O pins. The fault list of G 1 , G 2 , and G 3 ini- tially contains their local faults: C/ 0, A/ 1, and J/ 0. When we apply the first pat- tern, three events occur in the primary inputs: u 0onA , u 1onB ,and u 0 on C. They are good events because they happen in the good circuit. The output of good gate G 1 changes from unknown to one. In the presence of fault C/ 0, the output of faulty G 1 is the same as that of good G 1 . A bad gate is invisible if its faulty output is the same as the good output. The bad gates C/0 and J/0 are both invisible so they are not propagated to the subsequent stages. The output of G 2 changes from unknown to zero. In the presence of fault A/ 1, the faulty output changes from unknown to 1. Because the faulty output differs from the good output, bad gate A/ 1 becomes visible. A bad gate is visible
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Unformatted text preview: A /1 creates a bad event u → 1 on net H (in gray). A bad event does not occur in the good circuit; it only occurs in the faulty circuit of the corresponding fault. A new copy of bad gate A/ 1 is added to the concurrent fault list of G 4 because it has one input different from the good gate. It is said that bad gate A/ 1 diverges from its good gate. Finally, fault A/ 1 is detected because the faulty output K is different from the good output. At this time, we could drop detected fault A/ 1 but we keep it for illustration purposes. Figure 3.31 illustrates the concurrent fault simulation for test pattern P 2 . Two good events occur in this figure: 0 → 1 on C and 1 → 0 on B. The bad gate C/ 0, which A B C E F L H K J J /0 C /0 C /0: 1 → C /0: 0 → 1 C /0 A /1 A /1 G 1 G 3 G 2 G 4 → 1 1 → 1 1 1 1 1 1 1 0 0 1 C /0 1 C /0 ± FIGURE 3.31 Concurrent fault simulation ( P 2 )....
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