176_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

176_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - Logic...

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Logic and Fault Simulation 145 was invisible in pattern P 1 , now becomes newly visible. The newly visible bad gate creates a bad event—net E falls to zero, which in turn creates two divergences in G 2 and G 3 . The former is invisible but the latter creates a bad event—net J rises to one. Finally, the concurrent fault list of G 4 contains two bad gates; both faults A/ 1 and C/ 0 are detected. Again, we keep A/ 1 and C/ 0 faults for demonstrating the simulation of pattern P 3 . For the last test pattern P 3 (Figure 3.32), two good events occur at primary inputs A and C . The bad gate C/ 0 now becomes invisible. The bad gate C /0 is deleted from the concurrent fault list of G 3 . A bad gate converges to its good gate if it is not a local fault and its I/O values are identical to those of the good gate. Similarly, the other bad gates of C/ 0 also converge to G 2 and G 4 . Note that bad gate C/ 0 does not converge to G 1 because it is a local fault for G 1 . The bad gate A/ 1 can be examined in the same way. For gate G 3
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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