178_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 178_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - Logic...

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Logic and Fault Simulation 147 Good f 1 f 2 f k f k +1 f m P 1 P 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P i P i +1 P n G 1 F 1,1 F 1,2 F 1, i F 1, i +1 F 1, n F 2,1 F 2,2 F 2, i F 2, i +1 F 2, n F k ,1 F k ,2 F k , i F k , i +1 F k , n F k +1,1 F k +1,2 F k +1, i F k +1, i +1 F k +1, n F m ,1 F m ,2 F m , i F m , i +1 F m , n G 2 G i G i +1 G n ± FIGURE 3.34 Differential fault simulation. the states of the good circuit. Neither of the above two techniques is good for sequential fault simulation. Differential fault simulation combines the merits of concurrent fault simulation and single fault propagation techniques [Cheng 1989]. The idea is to simulate in turn every faulty circuit by tracking only the difference between a faulty circuit and the last simulated one. An event-driven simulator can easily implement differential fault simulation with the differences injected as
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## This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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