179_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

179_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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148 VLSI Test Principles and Architectures F collapsed fault list F empty? next pattern? restore good circuit state next fault? get next fault f 1. apply next pattern 2. O good good circuit outputs 1. restore faulty circuit state 2. remove last fault 3. inject fault f 4 . O f faulty circuit outputs 5. store state difference delete f from F end end yes yes yes yes no no no no start O f == O good ? ± FIGURE 3.35 Differential fault simulation flowchart. the state differences of its next undetected fault. This process repeats until there are no test patterns or no undetected faults. The problem with differential fault simulation is that the order of events caused
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Unformatted text preview: by fault sites is not the same as the order of the timing of their occurrence. If the circuit behavior depends on the gate delay of the circuit, the timing information of every event must be included. This solution, however, can potentially require high memory consumption. 3.4.6 Fault Detection In the previous sections, we defined fault detection as an output value being differ-ent from the good value. In the simple example we used to illustrate fault simulation...
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