180_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

180_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 149 techniques, making the fault detection decision is easy because the faults are hard detected ; that is, the outputs of the fault-free and faulty circuits are either 1 or 0 and are different. In practical cases, the fault detection decision is more difficult. For example, consider the stuck-at-zero fault that occurs at the enable input of a tristate buffer. With its enable input forced to 0, the tristate buffer’s output is in a floating state. It is unclear whether the fault is detected, because the logic value of a floating signal may be the same as the correct value by accident; however, if the fault is simulated against many test patterns, it is very likely that it will eventually be detected. For this reason, some fault simulators regard this kind of fault as poten- tially detected . Faults that cause the circuit to oscillate (called oscillation faults ) also complicate the fault detection decision because it is impossible to predict the faulty circuit outputs. Finally, some faults may cause the faulty circuit behavior
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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