183_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

183_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - K...

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152 VLSI Test Principles and Architectures 3.4.8.3 Critical Path Tracing Critical path tracing is another alternative to fault simulation [Abramovici 1984]. Given a test pattern t , net x has a critical value v if and only if the x stuck- at v ± fault is detected by t . A net that has a critical value is a critical net . The critical path is a path that consists of nets with critical values. Tracing the crit- ical path from PO to PI gives a list of critical nets and hence a list of detected faults. Critical path tracing is demonstrated in Figure 3.36. All the critical values are circled. The primary output K is certainly critical, as any change in K is observed. Both gate inputs H and J of gate G 4 are critical because flipping either one of them would change the primary output
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Unformatted text preview: K . It can be seen that E , F , A , and B are all critical. Note that L is not critical, because changing L would not change the primary output. After the critical path tracing, seven critical nets are identified and their associated faults ±A/ 1, H/ 1, B/ 0, E/ 0, F/ 0, J/ 1, K/ ² are detected. Special attention is needed when fanout branches reconverge. Figure 3.37 shows the example circuit for pattern P 3 . As is the case in pattern P 1 , nets K , J , and F A B C G 1 G 2 G 3 G 4 J L F E H K 1 1 1 1 1 ± FIGURE 3.36 Critical path tracing ± P 1 ² . A B C 1 G 1 G 2 G 3 G 4 J L F E H K 1 ± FIGURE 3.37 Critical path tracing ± P 3 ² ....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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