185_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

185_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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154 VLSI Test Principles and Architectures have detectability higher than 0.9 are actually detected, while less than 25% of faults that have a detectability lower than 0.1 are actually detected for single stuck-at fault test sets. 3.5 CONCLUDING REMARKS We have presented two fundamental subjects, logic simulation and fault simulation, that are important for readers to design quality digital circuits. Logic simulation checks whether the design will behave as predicted before its physical implementa- tion is built, while fault simulation tells us in advance how effective the given test pattern set is in detecting faults. For logic simulation, event-driven simulation that can take timing (delay) models and sequential circuit behavior into consideration is the technique most widely used in commercially available logic simulators. Examples of logic simulators include Verilog-XL, NC-Verilog (both from Cadence [Cadence 2006]), ModelSim (from Mentor Graphics [Mentor 2006]), and VCS (from Synopsys [Synopsys 2006]). These logic simulators can accept gate-level models as well as RTL and behav-
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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