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Logic and Fault Simulation 155 3.6 EXERCISES 3.1 (Parallel Gate Evaluation) Consider a logic simulator with four logic symbols (0, 1, u , and Z ) that are coded as follows: v 0 = ± 00 ² v 1 = ± 11 ² v u = ± 01 ² v Z = ± 10 ² Assume that the host computer has a word width of w . To simulate w input vectors in parallel, two words ( X 1 and X 2 ) are allocated for each signal X to store the first and second bits of the logic symbol codes, respectively. (a) Derive the gate evaluation procedures for AND, OR, and NOT operations. (b) Derive the evaluation procedures for complex gates such as a 2-to-1 mul- tiplexer, XOR, and tristate buffer. Note that the simulator is based on ternary logic; therefore,
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Unformatted text preview: Z-to-u conversions may be necessary to convert Z inputs to u ’s prior to gate evaluations. 3.2 (Timing Models) For circuit M shown in Figure 3.38, complete the following timing diagram (Figure 3.39) with respect to each timing model given below: (a) Nominal delay— Two-input gate, 1 ns; three-input gate, 1.2 ns; inverter, 0.6 ns. Inertial delay— All gates, 0.3 ns. (b) Rise delay— Two-input gate, 0.8 ns; three-input gate, 1 ns; inverter, 0.6 ns. Fall delay— Two-input gate, 1 ns; three-input gate, 1.2 ns; inverter, 0.8 ns. A B C E D J L F H ± FIGURE 3.38 Example circuit M ....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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