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Unformatted text preview: Z-to-u conversions may be necessary to convert Z inputs to u ’s prior to gate evaluations. 3.2 (Timing Models) For circuit M shown in Figure 3.38, complete the following timing diagram (Figure 3.39) with respect to each timing model given below: (a) Nominal delay— Two-input gate, 1 ns; three-input gate, 1.2 ns; inverter, 0.6 ns. Inertial delay— All gates, 0.3 ns. (b) Rise delay— Two-input gate, 0.8 ns; three-input gate, 1 ns; inverter, 0.6 ns. Fall delay— Two-input gate, 1 ns; three-input gate, 1.2 ns; inverter, 0.8 ns. A B C E D J L F H ± FIGURE 3.38 Example circuit M ....
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.
- Spring '08