187_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

187_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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156 VLSI Test Principles and Architectures A B C D E F H J L 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.5 4.0 0.1 0.4 ± FIGURE 3.39 The timing diagram. (c) Minimum delay— Two-input gate, 0.8 ns; three-input gate, 1 ns; inverter, 0.6 ns. Maximum delay— Two-input gate, 1 ns; three-input gate, 1.2 ns; inverter, 0.8 ns. 3.3 (Compiled-Code Simulation) Apply logic levelization on circuit M given in Figure 3.38. Assign a level number to each gate starting from level 1 at the primary inputs. Assume that a target machine can only support basic logic operations using two-input AND/OR and inversion. What is the pseudo code for circuit M if it is to be simulated in the target machine? 3.4 (Event-Driven Simulation) Redo Problem 3.2a using the nominal-delay event-driven simulation technique. Show all events and activity lists of each
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Unformatted text preview: time stamp. 3.5 (Hazard Detection) Use eight-valued logic to detect static and dynamic haz-ards in circuit M in response to an input change of ABC from {101} to {010}. 3.6 (Hazard Detection) For the circuit and test patterns given in Figure 3.40 below, determine whether there is a static or dynamic hazard, assuming there are no faults present in the design. 3.7 (Parallel-Pattern Single-Fault Propagation) For the circuit and two given stuck-at faults shown in Figure 3.40, use the parallel-pattern single-fault prop-agation fault simulation technique to identify which faults can be detected by the given test patterns....
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