188_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

188_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Logic and Fault Simulation 157 1 1 11 α stuck-at 0 β stuck-at 1 0 0 a b c ± FIGURE 3.40 Example circuit. A B C D G ± FIGURE 3.41 Circuit for Problem 3.9. 3.8 (Parallel Fault Simulation) Repeat Problem 3.7 using parallel fault simulation. 3.9 (Deductive Fault Simulation) Write the fault list propagation rule for the three-input NOR gate given in Figure 3.41. 3.10 (Deductive Fault Simulation) Repeat Problem 3.7 using deductive fault simulation. 3.11 (Concurrent Fault Simulation) Repeat Problem 3.7 using concurrent fault simulation. 3.12 (Critical Path Tracing) For the circuit in Problem 3.7, circle all the critical values for the three test patterns. What faults are detected?
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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