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158 VLSI Test Principles and Architectures 3.16 (A Design Practice) For the circuit given in Problem 3.7, use the fault simulation program (TurboFault) provided on the Web site to simulate the faulty output in the presence of fault ± . Is the fault detected? References R3.0—Books [Abramovici 1994] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design , IEEE Press, Piscataway, NJ, 1994 (revised printing). [Miczo 2003] A. Miczo, Digital Logic Testing and Simulation Hoboken, NJ, 2003. [Palnitkar 1996] S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis , Sunsoft, Mountain View, CA, 1996. [Thomas 2002] D. E. Thomas and P. R. Moorby, The Verilog Hardware Description Language , Springer Science, New York, 2002. [IEEE 1076-2002] IEEE Standard VHDL Language Reference Manual , IEEE Std. 1076-2002, Institute of Electrical and Electronics Engineers, New York, 2002. [IEEE 1463-2001]
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