190_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

190_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Logic and Fault Simulation 159 R3.4—Fault Simulation [Abramovici 1984] M. Abramovici, P. R. Menon, and D. T. Miller, Critical path tracing: An alternative to fault simulation, IEEE Des. Test Comput. , 1(1), 83–93, 1984. [Armstrong 1972] D. B. Armstrong, A deductive method for simulating faults in logic circuits, IEEE Trans. Comput. , C-21(5), 464–471, 1972. [Butler 1974] T. T. Butler, T. G. Hallin, J. J. Kulzer, and K. W. Johnson, LAMP: Application to switching system development, Bell System Tech. J. , 53, 1535–1555, 1974. [Cheng 1989] W. T. Cheng and M. L. Yu, Differential fault simulation: A fast method using minimal memory, in Proc. Des. Automat. Conf. , June 1989, pp. 424–428. [Goel 1980] P. Goel, Test generation cost analysis and projections, in Proc. Des. Automat. Conf. , June 1980, pp. 77–84. [Jain 1985] S. K. Jain and V. D. Agrawal, Statistical fault analysis, IEEE Des. Test Comput. , 2(1), 38–44, 1985. [Seshu 1965] S. Sesuh and D. N. Freeman, On improved diagnosis program,
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.
Ask a homework question - tutors are online