192_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

192_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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CHAPTER 4 T EST G ENERATION Michael S. Hsiao Virginia Tech, Blacksburg, Virginia ABOUT THIS CHAPTER Test generation is the task of producing an effective set of vectors that will achieve high fault coverage for a specified fault model. While much progress has been made over the years in automatic test pattern generation (ATPG), this problem remains an extremely difficult one. Without powerful ATPGs, chips will increasingly depend on design for testability (DFT) techniques to alleviate the high cost of generating vectors. This chapter deals with the fundamental issues behind the design of an ATPG, as well as the underlying learning mechanisms that can improve the overall performance of ATPG. This chapter is organized as follows. First, an overview of the problem of test generation is given, followed by random test generation. Next, deterministic algo- rithms for test generation for stuck-at faults are explained, including techniques that enhance the deterministic engines such as static and dynamic learning. Simulation-
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