194_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

194_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Test Generation 163 the fault d/ 0 is present it can be detected at the output e . Test generation attempts to generate test vectors for every possible fault in the circuit. In this example, in addition to the d/ 0 fault, faults such as a/ 1 ±b/ 1 ±c/ 0, etc. are also targeted by the test generator. As some of the fault in the circuit can be logically equivalent, no test can be obtained to distinguish between them. Thus, equivalent fault collapsing is often used to identify equivalent faults a priori in order to reduce the number of faults that must be targeted [Abramovici 1994] [Bushnell 2000] [Jha 2003]. Subsequently, the ATPG is only concerned with generating test vectors for each fault in the collapsed fault list. 4.2 RANDOM TEST GENERATION Random test generation (RTG) is one of the simplest methods for generating vectors. Vectors are randomly generated and fault-simulated (or fault-graded) on the circuit under test (CUT). Because no specific fault is targeted, the complexity of RTG is low. However, the disadvantages of RTG are that the test set size may
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