195_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES

# 195_pdfsam_VLSI TEST PRINCIPLES &amp; ARCHITECTURES -...

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164 VLSI Test Principles and Architectures ± FIGURE 4.3 Two equivalent circuits. output of the AND gate significantly increases. For example, if each input has a 75% probability of receiving a logic 1, then getting a logic 1 at the output of the AND gate now becomes 0 ± 75 8 = 0 ± 1001, rather than the previous 0.0039. Determining the optimal bias values for each primary input is not an easy task. Thus, rather than trying to obtain the optimal set of values, the objective is fre- quently to increase the probabilities for those difficult-to-control and difficult-to- observe nodes in the circuit. For instance, suppose a circuit has an eight-input AND gate; any fault that requires the AND gate output equal to logic 1 for detection will be considered difficult to test. It would then be beneficial to attempt to increase
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Unformatted text preview: the probability of obtaining a logic 1 at the output of this AND gate. Another issue regarding random test generation is the number of random vectors needed. Given a circuit with n primary inputs, there are clearly 2 n possible input vectors. One can express the probability of detecting fault f by any random vector to be: d f = T f 2 n where T f is the set of vectors that can detect fault f . Consequently, the probability that a random vector will not detect f ( i.e. , f escapes a random vector) is: e f = 1 − d f Therefore, given N random vectors, the probability that none of the N vectors detects fault f is: e N f = ² 1 − d f ³ N In other words, the probability that at least one out of N vectors will detect fault f is: 1 − ² 1 − d f ³ N...
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## This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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