199_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

199_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 168 VLSI Test Principles and Architectures w 1 xy = 1 w xy = 1 w x+y = 1 wx + wy = 1 Now, w can be expanded from the circuit shown in the figure to be w = yz. Plugging this into the equation above gives us: wx+wy = 1 yzx+yzy = 1 xyz+yz = 1 yz = 1 Therefore, the set of vectors that can detect w/0 is 001 101 . 4.3.1 Untestable Faults If the target fault is untestable, it would be impossible to satisfy Equation 4.2. Consider the circuit shown in Figure 4.6. Suppose the target fault is z/0. Then the set of vectors that can detect z/0 are those that can satisfy: z df =1 dz z f z = 1 f z = 0 z xy xy = 1 z0 = 1 UNSATISFIABLE df = 1, indicating dz =1 In other words, there exists no input vectors that can satisfy z that the fault z/0 is untestable. x y f z FIGURE 4.6 Example circuit for an untestable fault. ...
View Full Document

Ask a homework question - tutors are online